1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly relates to a semiconductor integrated circuit including a dynamic circuit.
2. Description of the Related Art
There has been conventionally known a semiconductor memory shown in FIG. 15 as a semiconductor integrated circuit. In the semiconductor memory, word driver 600 selects one of a plurality of word lines WL<0> . . . WL<n> (n is an integer not less than one), and the selected word line is activated so that data in memory cell 610 is outputted to bit lines BIT<0> and NBIT<0>. The data outputted to bit lines BIT<0> and NBIT<0> is amplified by sense amplifier 620 and is externally outputted as output signal DO<0>. Which one of the word lines is selected is determined in accordance with address signal Address and output of row decoder 630. If the output from row decoder 630 includes noise, a plurality of word lines can be possibly selected. When a plurality of word lines are selected, pieces of data outputted from memory cell 610, which is connected to the respective word lines, collide with each other on the bit lines. This leads to erroneous operation of the semiconductor memory.
A row decoder typically includes a dynamic circuit in order to increase outputting speed. The dynamic circuit thus used tends to generate noise in output. In order to reduce noise generated in output from a row decoder, there has been proposed a row decoder including a dynamic circuit, which also includes a holding circuit for holding voltage of an output node (see Unexamined Japanese Patent Publication No. 2003-318727, for example).